Known high-frequency switch circuits that are controlled by control potentials which are input as control signals employ field-effect transistors (FETs) or diodes. For example, Japanese Patent Laid-open Application No. 8-139014 (JP-A-08-139014) discloses a high-frequency switch circuit having a SPDT (Single-Pole, Double-Throw) structure which is made up of a plurality of cascaded FETs integrated on a GaAs substrate, as a semiconductor integrated circuit (IC).
FIG. 1 shows such a conventional SPDT circuit by way of example. The high-frequency switch circuit shown in FIG. 1 has three high-frequency terminals 901 to 903 and two control potential input terminals 911, 912 for being supplied with control potentials as control signals from an external circuit, high-frequency terminal 901 serving as a common terminal. N-channel FETs 931 to 935 having respective channels (drains-sources) connected in cascade are connected between high-frequency terminal 901 and high-frequency terminal 902. Similarly, N-channel FETs 936 to 940 having respective channels connected in cascade are connected between high-frequency terminal 901 and high-frequency terminal 903. FETs 931 to 940 have respective gates connected to ends of respective resistive elements 951 to 960. The opposite ends of resistive elements 951 to 955 that are connected to the gates of FETs 931 to 935 are connected in common to control signal input terminal 911, and the opposite ends of resistive elements 956 to 960 that are connected to the gates of FETs 936 to 940 are connected in common to control signal input terminal 912.
In this configuration, control potentials having binary levels, i.e., a high level and low level, are complementarily applied as control signals from an external circuit to control potential input terminals 911 and 912 for controlling the high-frequency switch circuit to perform switching operation. Specifically, when a high-level potential is applied to control potential input terminal 911 and a low-level potential is applied to control potential input terminal 912, FETs 931 to 935 are turned on and FETs 936 to 940 are turned off, connecting high-frequency terminals 901 and 902 to each other and disconnecting high-frequency terminals 901 and 903 from each other. Conversely, when a low-level potential is applied to control potential input terminal 911 and a high-level potential is applied to control potential input terminal 912, FETs 931 to 935 are turned off and FETs 936 to 940 are turned on, disconnecting high-frequency terminals 901 and 902 from each other and connecting high-frequency terminals 901, 903 to each other.
In recent years, devices equipped with high-frequency switch circuits are designed for being supplied with lower power supply voltages for lower electric power consumption, and hence control potentials to be applied to high-frequency switch circuits tend to be lower. The maximum handling power Pmax that can be handled by the conventional high-frequency switch circuit shown in FIG. 1 is expressed by:Pmax=2(n(VH−VL−VT))2/Z0  (1)where VH represents the high-level potential of switch control signal, VL the low-level potential of switch control signal, n the number of FETs connected in cascade, VT the threshold voltage of the FETs, and Z0 the impedance of the measuring system. When the high-level control potential of the switch becomes lower, VH in equation (1) becomes lower, resulting in a reduction in the handling power. Though the handling power can be increased by increasing the number of FETs connected in cascade, the increased number of FETs is liable to a corresponding increase in the chip area of the high-frequency switch circuit that is constructed as an integrated circuit.
Japanese Patent Laid-open Application No. 10-84267 (JP-A-10-084267) discloses a high-frequency switch circuit wherein, in the case of that the number n of cascaded FETs is 1, in order to substantially increase the control potential applied to the gate of the FET, a portion of a high-frequency signal that is input from a high-frequency signal path to the switch is detected to generate a DC potential proportional to the wave crest of the high-frequency signal, and the DC potential is applied as a control potential to the gate of the FET depending on a control signal from an external circuit.
The high-frequency switch circuit with a plurality of cascaded FETs is disadvantageous in that as the control potential is lowered, the handling power is lowered, and that if the handling power is to be increased, then the number of cascaded FETs is increased, resulting in an increase in the size of the high-frequency switch circuit constructed as an integrated circuit.
The high-frequency switch circuit as disclosed in JP-A-10-084267 is problematic in that in order to make a selection as to whether the DC potential generated from the high-frequency signal is to be applied to the gate of the FET or not, the FET for high-frequency switching and a selector circuit, i.e., the switch circuit and a power supply and a control signal for controlling the switch circuit, are required, with the result that the chip area of the high-frequency switch circuit constructed as an integrated circuit tends to increase.